Special Mode 4 (Sim Mode) (Uart2) - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

14.1.6 Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Table 14.18 lists the specifications of SIM mode. Table 14.19 lists the registers used in the SIM mode
and the register values set.
Table 14.18 SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
(2)
generation timing
Error detection
NOTES:
1. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC
register remains unchanged.
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to "1" (trans-
mission complete) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using
SIM mode, be sure to clear the IR bit to "0" (no interrupt request) after setting these bits.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register is set to "0" (internal clock) : fi/ (16(n+1))
fi = f , f , f
1SIO 2SIO
• The CKDIR bit is set to "1" (external clock
f : Input from CLK
EXT
• Before transmission can start, the following requirements must be met
_
The TE bit in the U2C1 register is set to "1" (transmission enabled)
_
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
• Before reception can start, the following requirements must be met
_
The RE bit in the U2C1 register is set to "1" (reception enabled)
_
Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit ="1")
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
(1)
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit in the the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD pin.
2
During transmission, a parity error is detected by the level of input to the R
when a transmission interrupt occurs
• Error sum flag
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
page 207
f o 3 8 5
Specification
, f . n: Setting value of U2BRG register
8SIO 32SIO
pin. n: Setting value of U2BRG register
2
00
) : f /16(n+1)
EXT
00
16
14. Serial I/O
to FF
16 16
to FF
16
D pin
X 2