Microblaze Core Configurability - Xilinx MicroBlaze Reference Manual

MicroBlaze Core Configurability

The MicroBlaze core has been developed to support a high degree of user configurability.
This allows tailoring of the processor to meet specific cost/performance requirements.
Configuration is done via parameters that typically enable, size, or select certain processor
features. For example, the instruction cache is enabled by setting the C_USE_ICACHE
parameter. The size of the instruction cache, and the cacheable memory range, are all
configurable using: C_CACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and
C_ICACHE_HIGHADDR respectively.
Parameters valid for the latest version of MicroBlaze are listed in
are recognized by older versions of MicroBlaze; however, the configurability is fully
backward compatible.
Shaded rows indicate that the parameter has a fixed value and cannot be modified.
Note:
Table 3-18: Configuration Parameters
Parameter Name
C_FAMILY
C_DATA_SIZE
C_ADDR_SIZE
C_DYNAMIC_BUS_SIZING
C_SCO
C_AREA_OPTIMIZED
C_OPTIMIZATION
C_INTERCONNECT
C_ENDIANNESS
1
C_BASE_VECTORS
C_FAULT_TOLERANT
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Target Family
Data Size
Data Side Address Size
Legacy
Xilinx internal
Select implementation
to optimize area with
lower instruction
throughput
Reserved for future use
Select interconnect
2 = AXI4 only
3 = AXI4 and ACE
Select endianness
1 = Little Endian
Configurable base
vectors
Implement fault
tolerance
www.xilinx.com
Table 3-18. Not all of these
Tool
Allowable Default
Assign
Values Value
Listed in virtex7 yes
Table 3-19
32 32 NA
32-64 32 NA
1 1 NA
0 0 NA
0, 1 0
0 0 NA
2, 3 2
1 1 yes
0x00000000- 0x0000
0xffffff80 0000
yes
0, 1 0
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VHDL Type
ed
string
integer
integer
integer
integer
integer
integer
integer
integer
std_logic_vector
integer
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