Floating Point Unit (Fpu) - Xilinx MicroBlaze Reference Manual

Floating Point Unit (FPU)

Overview
The MicroBlaze floating point unit is based on the
• Uses IEEE 754 single precision floating point format, including definitions for infinity,
not-a-number (NaN), and zero
• Supports addition, subtraction, multiplication, division, comparison, conversion and
square root instructions
• Implements round-to-nearest mode
• Generates sticky status bits for: underflow, overflow, divide-by-zero and invalid
operation
For improved performance, the following non-standard simplifications are made:
• Denormalized
denormalized number returns a quiet NaN and sets the sticky denormalized operand
error bit in FSR;
• A denormalized result is stored as a signed 0 with the underflow bit set in FSR. This
method is commonly referred to as Flush-to-Zero (FTZ)
• An operation on a quiet NaN returns the fixed NaN: 0xFFC00000, rather than one of the
NaN operands
• Overflow as a result of a floating point operation always returns signed ∞
Format
An IEEE 754 single precision floating point number is composed of the following three
fields:
1. 1-bit sign
2. 8-bit biased exponent
3. 23-bit fraction (a.k.a. mantissa or significand)
1. Numbers that are so close to 0, that they cannot be represented with full precision, that is, any number n that falls in the
following ranges: ( 1.17549*10
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
(1)
operands are not supported. A hardware floating point operation on a
see "Floating Point Status Register (FSR)" on page 30
-38
> n > 0 ), or ( 0 > n > -1.17549 * 10
www.xilinx.com
Chapter 2: MicroBlaze Architecture
IEEE 754-1985 standard:
-38
)
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