Xilinx MicroBlaze Reference Manual page 260

32-bit soft processor
Hide thumbs Also See for MicroBlaze:
Table of Contents

Advertisement

rtsd
Return from Subroutine
rtsd
1 0 1 1 0 1 1 0 0 0 0
0
6
Description
Return from subroutine will branch to the location specified by the contents of rA plus the IMM
field, sign-extended to 32 bits.
This instruction always has a delay slot. The instruction following the RTSD is always executed
before the branch target.
Pseudocode
(rA) + sext(IMM)
PC
allow following instruction to complete execution
Registers Altered
PC
Latency
1 cycle (if successful branch prediction occurs)
2 cycles (with Branch Target Cache disabled)
3 cycles (if branch prediction mispredict occurs)
Note
Convention is to use general purpose register r15 as rA.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rA, IMM
rA
1
1
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
IMM
1
6
3
1
260
Send Feedback

Advertisement

Table of Contents
loading

Table of Contents