Xilinx MicroBlaze Reference Manual page 165

Table 3-18: Configuration Parameters (Cont'd)
Parameter Name
C_BRANCH_TARGET_CACHE_SIZE
C_M_AXI_DP_
THREAD_ID_WIDTH
C_M_AXI_DP_DATA_WIDTH
C_M_AXI_DP_ADDR_WIDTH
C_M_AXI_DP_
SUPPORTS_THREADS
C_M_AXI_DP_SUPPORTS_READ
C_M_AXI_DP_SUPPORTS_WRITE
C_M_AXI_DP_SUPPORTS_
NARROW_BURST
C_M_AXI_DP_PROTOCOL
C_M_AXI_DP_
EXCLUSIVE_ACCESS
C_M_AXI_IP_
THREAD_ID_WIDTH
C_M_AXI_IP_DATA_WIDTH
C_M_AXI_IP_ADDR_WIDTH
C_M_AXI_IP_
SUPPORTS_THREADS
C_M_AXI_IP_SUPPORTS_READ
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Branch Target Cache
3
size:
0 = Default
1 = 8 entries
2 = 16 entries
3 = 32 entries
4 = 64 entries
5 = 512 entries
6 = 1024 entries
7 = 2048 entries
Data side AXI thread ID
width
Data side AXI data width
Data side AXI address
width
Data side AXI uses
threads
Data side AXI support
for read accesses
Data side AXI support
for write accesses
Data side AXI narrow
burst support
Data side AXI protocol
Data side AXI exclusive
access support
Instruction side AXI
thread ID width
Instruction side AXI data
width
Instruction side AXI
address width
Instruction side AXI uses
threads
Instruction side AXI
support for read
accesses
www.xilinx.com
Tool
Allowable Default
Assign
Values Value
ed
0-7 0
1 1
32 32
32-64 32 yes
0 0
1 1
1 1
0 0
AXI4, AXI4 yes
AXI4LITE LITE
0,1 0
1 1
32 32
32 32
0 0
1 1
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VHDL Type
integer
integer
integer
integer
integer
integer
integer
integer
string
integer
integer
integer
integer
integer
integer
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