Xilinx MicroBlaze Reference Manual page 240

To refer to special purpose registers in assembly language, use rmsr for MSR, rfsr for FSR, rslr for
SLR, rshr for SHR, rpid for PID, rzpr for ZPR, rtlblo for TLBLO, rtlbhi for TLBHI, rtlbx for TLBX, and
rtlbsx for TLBSX.
The PC, ESR, EAR, BTR, EDR and PVR0 - PVR12 cannot be written by the MTS instruction.
The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0.
The SLR and SHR are only valid as a destination if the MicroBlaze parameter
C_USE_STACK_PROTECTION
PID, ZPR and TLBSX are only valid as destinations when the parameter C_USE_MMU > 1 (User
Mode) and the parameter C_MMU_TLB_ACCESS > 1 (Read). TLBLO, TLBHI and TLBX are only valid as
destinations when the parameter C_USE_MMU > 1 (User Mode).
When changing MSR[VM] or PID the instruction must always be followed by a synchronizing
branch instruction, for example BRI 4.
After writing to TLBHI in order to invalidate one or more UTLB entries, an MBAR 1 instruction must
be issued to ensure that coherency is preserved in a coherent multi-processor system.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 5: MicroBlaze Instruction Set Architecture
is set to 1.
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