Xilinx MicroBlaze Reference Manual page 49

cache needs to do memory accesses). When
write latency normally is two cycles (more if the posted-write buffer in the memory
controller is full).
The MicroBlaze instruction and data caches can be configured to use 4, 8 or 16 word cache
lines. When using a longer cache line, more bytes are prefetched, which generally improves
performance for software with sequential access patterns. However, for software with a
more random access pattern the performance can instead decrease for a given cache size.
This is caused by a reduced cache hit rate due to fewer available cache lines.
For details on the different memory interfaces refer to
Interface Description.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_DCACHE_USE_WRITEBACK
Chapter 3, MicroBlaze Signal
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Chapter 2: MicroBlaze Architecture
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