Xilinx MicroBlaze Reference Manual page 185

andni
Logical AND NOT with Immediate
andni
1 0 1 0 1 1
0 6
Description
The IMM field is sign-extended to 32 bits. The contents of register rA are ANDed with the logical
complement of the extended IMM field; the result is placed into register rD.
Pseudocode
←
(rD) (rA)
Registers Altered
• rD
Latency
1 cycle
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B
instruction with an imm instruction. See the instruction
bit immediate values.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, IMM
rD rA
1
1
∧
(sext(IMM))
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
IMM
1
6
"imm," page 222
3
1
for details on using 32-
185
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