Xilinx MicroBlaze Reference Manual page 252

Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
←
x FSLx
if x >= C_FSL_LINKS then
←
x 0
Mx_AXIS_TDATA
if (n = 1) then
MSR[Carry]
Mx_AXIS_TLAST
Registers Altered
• MSR[Carry]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 1 cycle with
• 2 cycles with
The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can
be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1,
and the instruction is not atomic.
Note
To refer to an FSLx interface in assembly language, use rfsl0, rfsl1, ... rfsl15.
The blocking versions of this instruction should not be placed in a delay slot when the parameter
C_USE_EXTENDED_FSL_INSTR
These instructions are only available when the MicroBlaze parameter C_FSL_LINKS is greater than 0.
The extended instructions (test and atomic versions) are only available when the MicroBlaze
parameter C_USE_EXTENDED_FSL_INSTR is set to 1.
It is not recommended to allow these instructions in user mode, unless absolutely necessary for
performance reasons, since that removes all hardware protection preventing incorrect use of a link.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
00111
←
(rA)
← ∧
Mx_AXIS_TVALID
←
C
=0
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
is set to 1, since this prevents interrupts from being served.
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Chapter 5: MicroBlaze Instruction Set Architecture
Mx_AXIS_TREADY
252
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