Xilinx MicroBlaze Reference Manual page 41

Table 2-26: Processor Version Register 2 (PVR2) (Cont'd)
Bits Name
14 MSR
15 PCMP
16 AREA
17 BS
18 DIV
19 MUL
20 FPU
21 MUL64
22 FPU2
23 IMPEXC
24 Reserved
25 OP0EXC
26 UNEXC
27 OPEXC
28 AXIDEXC
29 AXIIEXC
30 DIVEXC
31 FPUEXC
Table 2-27: Processor Version Register 3 (PVR3)
Bits Name
0 DEBUG
1 EXT_DEBUG Use extended debug logic
2 Reserved
3:6 PCBRK
7:9 Reserved
10:12 RDADDR
13:15 Reserved
16:18 WRADDR
19 Reserved
20:24 FSL
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Description
Use msrset and msrclr instructions
Use pattern compare and CLZ instructions
Select implementation to optimize area
with lower instruction throughput
Use barrel shifter
Use divider
Use hardware multiplier
Use FPU
Use 64-bit hardware multiplier
Use floating point conversion and square
root instructions
Allow imprecise exceptions for ECC errors
in LMB memory
Generate exception for 0x0 illegal opcode
Generate exception for unaligned data
access
Generate exception for any illegal opcode
Generate exception for M_AXI_D error
Generate exception for M_AXI_I error
Generate exception for division by zero or
division overflow
Generate exceptions from FPU
Description
Use debug logic
Number of PC breakpoints
Number of read address breakpoints
Number of write address breakpoints
Number of AXI4-Stream links
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Value
C_USE_MSR_INSTR
C_USE_PCMP_INSTR
C_AREA_OPTIMIZED = 1 (Area)
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
C_USE_FPU > 0 (None)
C_USE_HW_MUL = 2 (Mul64)
C_USE_FPU = 2 (Extended)
C_IMPRECISE_EXCEPTIONS
0
C_OPCODE_0x0_ILLEGAL
C_UNALIGNED_EXCEPTIONS
C_ILL_OPCODE_EXCEPTION
C_M_AXI_D_BUS_EXCEPTION
C_M_AXI_I_BUS_EXCEPTION
C_DIV_ZERO_EXCEPTION
C_FPU_EXCEPTION
Value
C_DEBUG_ENABLED > 0
C_DEBUG_ENABLED = 2 (Extended)
C_NUMBER_OF_PC_BRK
C_NUMBER_OF_RD_ADDR_BRK
C_NUMBER_OF_WR_ADDR_BRK
0
C_FSL_LINKS
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