Xilinx MicroBlaze Reference Manual page 257

rtbd
Return from Break
rn from Interrupt
rtbd
1 0 1 1 0 1 1 0 0 1 0
0 6
Description
Return from break will branch to the location specified by the contents of rA plus the IMM field,
sign-extended to 32 bits. It will also enable breaks after execution by clearing the BIP flag in the
MSR.
This instruction always has a delay slot. The instruction following the RTBD is always executed
before the branch target. That delay slot instruction has breaks disabled.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged.
This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged
Instruction exception occurs.
Pseudocode
if MSR[UM] = 1 then
ESR[EC]
else
←
(rA) + sext(IMM)
PC
allow following instruction to complete execution
MSR[BIP]
MSR[UM]
MSR[VM]
Registers Altered
• PC
• MSR[BIP], MSR[UM], MSR[VM]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 2 cycles
Note
Convention is to use general purpose register r16 as rA.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rA, IMM
rA
11
←
00111
←
0
←
MSR[UMS]
←
MSR[VMS]
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Chapter 5: MicroBlaze Instruction Set Architecture
IMM
16 31
257
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