Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze Architecture
This chapter contains an overview of MicroBlaze™ features and detailed information on
MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit
general purpose registers, virtual-memory management, cache software support, and
AXI4-Stream interfaces.

Overview

The MicroBlaze™ embedded processor soft core is a reduced instruction set computer
(RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs).
Figure 2-1 shows a functional block diagram of the MicroBlaze core.
Instruction-side
bus interface
M_AXI_IC
M_ACE_IC
M_AXI_IP
Bus
IF
ILMB
Optional MicroBlaze feature
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Memory Management Unit (MMU)
UTLB
ITLB
Program
Counter
Special
Purpose
Registers
Branch
Target
Cache
Instruction
Buffer
Instruction
Decode
Figure 2-1: MicroBlaze Core Block Diagram
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Data-side
bus interface
DTLB
ALU
Shift
Barrel Shift
Multiplier
Divider
FPU
Bus
IF
Register File
32 X 32b
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M_AXI_DC
M_ACE_DC
M_AXI_DP
DLMB
M0_AXIS..
M15_AXIS
S0_AXIS..
S15_AXIS
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