Xilinx MicroBlaze Reference Manual page 67

ESR[DS] bit is set. In this case the exception handler should resume execution from the
branch target address stored in BTR.
The EE and EIP bits in MSR are automatically reverted when executing the
The VM and UM bits in MSR are automatically reverted from VMS and UMS when executing
the , , and
RTED RTBD
Exception Priority
When two or more exceptions occur simultaneously, they are handled in the following
order, from the highest priority to the lowest:
• Instruction Bus Exception
• Instruction TLB Miss Exception
• Instruction Storage Exception
• Illegal Opcode Exception
• Privileged Instruction Exception or Stack Protection Violation Exception
• Data TLB Miss Exception
• Data Storage Exception
• Unaligned Exception
• Data Bus Exception
• Divide Exception
• FPU Exception
• Stream Exception
Exception Causes
• Stream Exception
The AXI4-Stream exception is caused by executing a
bit set to '1' when there is a control bit mismatch.
• Instruction Bus Exception
The instruction bus exception is caused by errors when reading data from memory.
The instruction peripheral AXI4 interface (M_AXI_IP) exception is caused by an error
¨
response on
The instruction cache AXI4 interface (M_AXI_IC) is caused by an error response on
¨
M_AXI_IC_RRESP
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
instructions.
RTID
.
M_AXI_IP_RRESP
. The exception can only occur when
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Chapter 2: MicroBlaze Architecture
RTED
or instruction with the 'e'
get getd
C_ICACHE_ALWAYS_USED
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instruction.
is set
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