Core Description - Xilinx CAN FD v2.0 Product Manual

Core Description

The core functions are divided into two independent layers as shown in
object layer interfaces with the host control through the AXI4-Lite/APB interface and works
in the AXI4-Lite/APB clock domain. The transfer layer interfaces with the external PHY and
operates in the CAN clock domain. Information exchange between the two layers is done
through the CDC synchronizers. The CAN FD object layer provides a state-of-the-art
transmission and reception method to manage message buffers.
Object Layer (Logical Link Layer)
The object layer is divided into the following submodules:
• Register Module – This module allows for read and write access to the registers
through the external host interface.
• TX Buffer Management Module – The TX Buffer Management Module (TBMM)
interfaces with the CAN FD protocol engine to provide the next buffer to transmit on
the CAN bus. It manages the host access to the TX block RAM.
• RX Buffer Management Module – The RX Buffer Management Module (RBMM)
interfaces with the CAN FD protocol engine to provide storage for message reception
from the CAN bus. It manages the host access to the RX block RAM.
Transfer Layer (Medium Access Control Layer)
The transfer layer provides the following main functions:
• Initiation of the transmission process after recognizing bus idle (compliance with
inter-frame space)
Serialization of the frame
°
Bit stuffing
°
Arbitration and passing into receive mode in case of loss of arbitration
°
ACK check
°
Presentation of a serial bitstream to PHY for transmission
°
CRC sequence calculation including stuff bit count for FD frames
°
Bit rate switching
°
• Reception of a serial bitstream from the PHY
Deserialization and recompiling of the frame structure
°
Bit destuffing
°
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 1: Overview
Figure 1-1. The
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