Xilinx MicroBlaze Reference Manual page 245

muli
Multiply Immediate
muli
0 1 1 0 0 0
0 6
Description
Multiplies the contents of registers rA and the value IMM, sign-extended to 32 bits; and puts the
result in register rD. This is a 32-bit by 32-bit multiplication that will produce a 64-bit result. The
least significant word of this value is placed in rD. The most significant word is discarded.
Pseudocode
←
(rD)
Registers Altered
• rD
Latency
• 1 cycle with
• 3 cycles with
Notes
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits
to use as the immediate operand. This behavior can be overridden by preceding the Type B
instruction with an imm instruction. See the instruction
bit immediate values.
This instruction is only valid if the target architecture has multiplier primitives, and if present, the
MicroBlaze parameter C_USE_HW_MUL is greater than 0.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, IMM
rD rA
1
1
×
LSW( (rA) sext(IMM) )
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
1
6
=0
=1
"imm," page 222
IMM
for details on using 32-
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