Xilinx MicroBlaze Reference Manual page 16

Table 2-6: MicroBlaze Instruction Set Summary (Cont'd)
Type A
Type B
MTS Sd,Ra 100101
MFS Rd,Sa
100101
MFSE Rd,Sa 100101
MSRCLR Rd,Imm 100101
MSRSET Rd,Imm 100101
BR Rb
100110
BRD Rb 100110
BRLD Rd,Rb 100110
BRA Rb 100110
BRAD Rb 100110
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
0-5 6-10 11-15 16-20
0-5 6-10 11-15
00000 Ra
Rd 00000
Rd 01000
Rd 00001
Rd 00000
00000 00000 Rb
00000 10000 Rb
Rd 10100 Rb
00000 01000 Rb
00000 11000 Rb
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Chapter 2: MicroBlaze Architecture
21-31
16-31
11 & Sd SPR[Sd] := Ra, where:
· SPR[0x0001] is MSR
· SPR[0x0007] is FSR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO
· SPR[0x1004] is TLBHI
· SPR[0x1005] is TLBSX
Rd := SPR[Sa], where:
10 & Sa
· SPR[0x0000] is PC
· SPR[0x0001] is MSR
· SPR[0x0003] is EAR[31:0]
· SPR[0x0005] is ESR
· SPR[0x0007] is FSR
· SPR[0x000B] is BTR
· SPR[0x000D] is EDR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO
· SPR[0x1004] is TLBHI
· SPR[0x2000 to 200B] is PVR[0 to 12]
10 & Sa Rd := SPR[Sa][63:32], where:
· SPR[0x0003] is EAR[63:32]
· SPR[0x2008] is PVR[8][63:32]
· SPR[0x2009] is PVR[9][63:32]
00 & Imm14 Rd := MSR
MSR := MSR and Imm14
00 & Imm14 Rd := MSR
MSR := MSR or Imm14
00000000000 PC := PC + Rb
00000000000 PC := PC + Rb
00000000000 PC := PC + Rb
Rd := PC
00000000000 PC := Rb
00000000000 PC := Rb
Semantics
16
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