Xilinx MicroBlaze Reference Manual page 163

Table 3-18: Configuration Parameters (Cont'd)
Parameter Name
C_ADDR_TAG_BITS
C_CACHE_BYTE_SIZE
C_DCACHE_BASEADDR
C_DCACHE_HIGHADDR
C_USE_DCACHE
C_ALLOW_DCACHE_WR
C_DCACHE_LINE_LEN
C_DCACHE_ALWAYS_USED
C_DCACHE_FORCE_TAG_LUTRAM
C_DCACHE_USE_WRITEBACK
C_DCACHE_VICTIMS
C_DCACHE_DATA_WIDTH
C_DCACHE_ADDR_TAG
C_DCACHE_BYTE_SIZE
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Instruction cache
address tags
Instruction cache size
Data cache base address
Data cache high address
Data cache
Data cache write enable
Data cache line length
Data cache interface
used for all accesses in
the cacheable range
Data cache tag always
implemented with
distributed RAM
Data cache write-back
storage policy used
Data cache victims
Data cache data width
0 = 32 bits
1 = Full cache line
2 = 512 bits
Data cache address tags
Data cache size
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Tool
Allowable Default
Assign
Values Value
0-25 17
64, 128, 256,
512, 1024,
2048, 4096,
8192
8192, 16384,
32768,
2
65536
0x00000000 0x0000
- 0xFFFFFFFF 0000
0x00000000 0x3FFF
- 0xFFFFFFFF FFFF
0, 1 0
0, 1 1
4, 8, 16 4
0, 1 1
0, 1 0
0, 1 0
0, 2, 4, 8 0
0, 1, 2 0
0-25 17
64, 128, 256,
512, 1024,
2048, 4096,
8192
8192, 16384,
32768,
2
65536
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VHDL Type
ed
yes
integer
integer
std_logic_vector
std_logic_vector
integer
integer
integer
integer
integer
integer
integer
integer
yes
integer
integer
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