Xilinx MicroBlaze Reference Manual page 235

mfs
Move From Special Purpose Register
mfs
mfse
1 0 0 1 0 1
0 6
Description
Copies the contents of the special purpose register rS into register rD. The special purpose
registers TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.
If the E bit is set, the extended part of the special register is moved. The EAR, PVR[8] and PVR[9}
registers have extended parts when extended addressing is enabled ( C_ADDR_SIZE > 32).
Pseudocode
if E = 1 then
switch (rS):
case 0x0003 : (rD)
case 0x2008 : (rD)
case 0x2009 : (rD)
default : (rD)
else
switch (rS):
case 0x0000 : (rD)
case 0x0001 : (rD)
case 0x0003 : (rD)
case 0x0005 : (rD)
case 0x0007 : (rD)
case 0x000B : (rD)
case 0x000D : (rD)
case 0x0800 : (rD)
case 0x0802 : (rD)
case 0x1000 : (rD)
case 0x1001 : (rD)
case 0x1002 : (rD)
case 0x1003 : (rD)
case 0x1004 : (rD)
case 0x200x : (rD)
default : (rD)
Registers Altered
• rD
Latency
• 1 cycle
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rS
rD, rS
rD 0 E 0 0 0 1 0
11
←
EAR[0:C_ADDR_SIZE-32-1]
←
PVR8[0:C_ADDR_SIZE-32-1]
←
PVR9[0:C_ADDR_SIZE-32-1]
←
Undefined
←
PC
←
MSR
←
EAR[C_ADDR_SIZE-32:C_ADDR_SIZE-1]
←
ESR
←
FSR
←
BTR
←
EDR
←
SLR
←
SHR
←
PID
←
ZPR
←
TLBX
←
TLBLO
←
TLBHI
←
PVRx[C_ADDR_SIZE-32:C_ADDR_SIZE-1] (where x = 0 to 12)
←
Undefined
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Chapter 5: MicroBlaze Instruction Set Architecture
16 18
rS
31
235
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