Xilinx MicroBlaze Reference Manual page 31

The contents of this register is undefined for all other exceptions. When read with the MFS
instruction, the EDR is specified by setting Sa = 0x000D.
register and Table 2-15
The register is only implemented if C_FSL_LINKS is greater than 0 and C_FSL_EXCEPTION is
Note:
set to 1.
0
Table 2-15: Exception Data Register (EDR)
Bits Name
0:31 EDR
Stack Low Register (SLR)
The Stack Low Register stores the stack low limit use to detect stack overflow. When the
address of a load or store instruction using the stack pointer (register R1) as rA is less than
the Stack Low Register, a stack overflow occurs, causing a Stack Protection Violation
exception if exceptions are enabled in MSR.
When read with the MFS instruction, the SLR is specified by setting Sa = 0x0800.
Figure 2-10 illustrates the SLR register and
values.
The register is only implemented if stack protection is enabled by setting the parameter
Note:
C_USE_STACK_PROTECTION
no effect.
Stack protection is not available when the MMU is enabled (C_USE_MMU > 0). With the MMU
Note:
page-based memory protection is provided through the UTLB instead.
0
Table 2-16: Stack Low Register (SLR)
Bits Name
0:31 SLR
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
provides bit descriptions and reset values.
Figure 2-9: EDR
Exception Data Register
to 1. If stack protection is not implemented, writing to the register has
Figure 2-10: SLR
Stack Low Register
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Figure 2-9
↑
EDR
Description
Table 2-16 provides bit descriptions and reset
↑
SLR
Description
illustrates the EDR
31
Reset Value
0x00000000
31
Reset Value
0x00000000
31
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