Xilinx MicroBlaze Reference Manual page 167

Table 3-18: Configuration Parameters (Cont'd)
Parameter Name
C_M_AXI_DC_
EXCLUSIVE_ACCESS
C_M_AXI_DC_USER_VALUE
C_M_AXI_IC_
THREAD_ID_WIDTH
C_M_AXI_IC_DATA_WIDTH
C_M_AXI_IC_ADDR_WIDTH
C_M_AXI_IC_
SUPPORTS_THREADS
C_M_AXI_IC_SUPPORTS_READ
C_M_AXI_IC_SUPPORTS_WRITE
C_M_AXI_IC_SUPPORTS_
NARROW_BURST
C_M_AXI_IC_SUPPORTS_
USER_SIGNALS
C_M_AXI_IC_PROTOCOL
C_M_AXI_IC_AWUSER_WIDTH
C_M_AXI_IC_ARUSER_WIDTH
C_M_AXI_IC_WUSER_WIDTH
C_M_AXI_IC_RUSER_WIDTH
C_M_AXI_IC_BUSER_WIDTH
C_M_AXI_IC_USER_VALUE
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Data cache AXI exclusive
access support
Data cache AXI user
value
Instruction cache AXI ID
width
Instruction cache AXI
data width
Instruction cache AXI
address width
Instruction cache AXI
uses threads
Instruction cache AXI
support for read
accesses
Instruction cache AXI
support for write
accesses
Instruction cache AXI
narrow burst support
Instruction cache AXI
user signal support
Instruction cache AXI
protocol
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user value
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Tool
Allowable Default
Assign
Values Value
ed
0,1 0
0-31 31
1 1
32, 64, 128,
32
256, 512
32 32
0 0
1 1
0 0
0 0
1 1
AXI4 AXI4
5 5
5 5
1 1
1 1
1 1
0-31 31
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VHDL Type
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
string
integer
integer
integer
integer
integer
integer
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