Xilinx MicroBlaze Reference Manual page 81

Victim Cache
The victim cache is enabled by setting the parameter
defines the number of cache lines that can be stored in the victim cache. Whenever a
complete cache line is evicted from the cache, it is saved in the victim cache. By saving the
most recent lines they can be fetched much faster, should the processor request them,
thereby improving performance. If the victim cache is not used, all evicted cache lines must
be read from memory again when they are needed.
With the AXI4 interface,
from/to the victim cache each clock cycle, either 32 bits or an entire cache line.
Note that to be able to use the victim cache, write-back must be enabled and area
optimization must not be enabled.
Data Cache Software Support
MSR Bit
The DCE bit in the MSR controls whether or not the cache is enabled. When disabling
caches the user must ensure that all the prior writes within the cacheable range have been
completed in external memory before reading back over M_AXI_DP. This can be done by
writing to a semaphore immediately before turning off caches, and then in a loop poll until
it has been written.
The contents of the cache are preserved when the cache is disabled.
WDC Instruction
The optional WDC instruction (
lines in the data cache from an application. For a detailed description, please refer to
Chapter 5, MicroBlaze Instruction Set
The WDC instruction can also be used together with parity protection to periodically
invalidate entries the cache, to avoid accumulating errors.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_DCACHE_DATA_WIDTH
C_ALLOW_DCACHE_WR=1
Architecture.
www.xilinx.com
Chapter 2: MicroBlaze Architecture
C_DCACHE_VICTIMS
determines the amount of data transferred
) is used to invalidate or flush cache
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