Xilinx MicroBlaze Reference Manual page 281

other cache lines are not inadvertently invalidated, erroneously discarding data that has not yet been
written to memory.
The address of the affected cache line is always the physical address, independent of the parameter
and whether the MMU is in virtual mode or real mode.
C_USE_MMU
When using wdc.flush in a loop to flush the entire cache, the loop can be optimized by using rA as
the cache base address and rB as the loop counter:
addik
addik
loop: wdc.flush r5,r6
bgtid
addik
When using wdc.clear in a loop to invalidate a memory area in the cache, the loop can be optimized
by using rA as the memory area base address and rB as the loop counter:
addik
addik
loop: wdc.clear r5,r6
bgtid
addik
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
r5,r0,C_DCACHE_BASEADDR
r6,r0,C_DCACHE_BYTE_SIZE-C_DCACHE_LINE_LEN*4
r6,loop
r6,r6,-C_DCACHE_LINE_LEN*4
r5,r0,memory_area_base_address
r6,r0,memory_area_byte_size-C_DCACHE_LINE_LEN*4
r6,loop
r6,r6,-C_DCACHE_LINE_LEN*4
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Chapter 5: MicroBlaze Instruction Set Architecture
281
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