Xilinx MicroBlaze Reference Manual page 156

Signal Name
1
Trace_Data_Read
1
Trace_Data_Write
Trace_DCache_Req
Trace_DCache_Hit
Trace_DCache_Rdy
,4
Trace_DCache_Read
Trace_ICache_Req
Trace_ICache_Hit
Trace_ICache_Rdy
Trace_OF_PipeRun
3
Trace_EX_PipeRun
3
Trace_MEM_PipeRun
Trace_MB_Halted
1. Valid only when Trace_Valid_Instr = 1
2. Valid only when Trace_Exception_Taken = 1
3. Not used with area optimization feature
4. Valid only when Trace_DCache_Req = 1
Table 3-16: Mapping of Trace MSR
Trace_MSR_Reg
Bit
0
1
2
3
4
5
6
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Table 3-15: MicroBlaze Trace Signals (Cont'd)
Description
D-side memory access is a read
D-side memory access is a write
Data memory address is within D-
Cache range
Data memory address is present in D-
Cache
Data memory address is within D-
Cache range and the access is
completed
The D-Cache request is a read
Instruction memory address is within
I-Cache range, and the cache is enabled
in the Machine Status Register
Instruction memory address is present
in
I-Cache
Instruction memory address is within
I-Cache range and the access is
completed
Pipeline advance for Decode stage
Pipeline advance for Execution stage
Pipeline advance for Memory stage
Pipeline is halted by debug
Bit Name
17 VMS
18 VM
19 UMS
20 UM
21 PVR
22 EIP
23 EE
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Chapter 3: MicroBlaze Signal Interface Description
VHDL Type
Machine Status Register
Description
Virtual Protected Mode Save
Virtual Protected Mode
User Mode Save
User Mode
Processor Version Register exists
Exception In Progress
Exception Enable
Direction
std_logic output
output
std_logic
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
output
std_logic
156
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