Xilinx MicroBlaze Reference Manual page 32

Stack High Register (SHR)
The Stack High Register stores the stack high limit use to detect stack underflow. When the
address of a load or store instruction using the stack pointer (register R1) as rA is greater
than the Stack High Register, a stack underflow occurs, causing a Stack Protection Violation
exception if exceptions are enabled in MSR.
When read with the MFS instruction, the SHR is specified by setting Sa = 0x0802.
Figure 2-11 illustrates the SHR register and
values.
The register is only implemented if stack protection is enabled by setting the parameter
Note:
C_USE_STACK_PROTECTION
no effect.
Stack protection is not available when the MMU is enabled (C_USE_MMU > 0). With the MMU
Note:
page-based memory protection is provided through the UTLB instead.
0
Table 2-17: Stack High Register (SHR)
Bits Name
0:31 SHR
Process Identifier Register (PID)
The Process Identifier Register is used to uniquely identify a software process during MMU
address translation. It is controlled by the
The register is only implemented if
C_AREA_OPTIMIZED
instructions, the PID is specified by setting Sa = 0x1000. The register is accessible according
to the memory management special registers parameter
PID is also used when accessing a TLB entry:
• When writing Translation Look-Aside Buffer High (TLBHI) the value of PID is stored in
the TID field of the TLB entry
• When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID
Figure 2-12 illustrates the PID register and
values.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
to 1. If stack protection is not implemented, writing to the register has
Figure 2-11: SHR
Stack High Register
C_USE_MMU
is set to 0 (Performance). When accessed with the MFS and MTS
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Chapter 2: MicroBlaze Architecture
Table 2-17 provides bit descriptions and reset
↑
SHR
Description
configuration option on MicroBlaze.
C_USE_MMU
is greater than 1 (User Mode) and
C_MMU_TLB_ACCESS
Table 2-18 provides bit descriptions and reset
31
Reset Value
0xFFFFFFFF
.
32
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