Xilinx MicroBlaze Reference Manual page 91

Table 2-40: MicroBlaze Performance Monitoring Events
Event
0 Any valid instruction executed
1 Load word (lw, lwi, lwx) executed
2 Load halfword (lhu, lhui) executed
3 Load byte (lbu, lbui) executed
4 Store word (sw, swi, swx) executed
5 Store halfword (sh, shi) executed
6 Store byte (sb, sbi) executed
7 Unconditional branch (br, bri, brk, brki) executed
8 Taken conditional branch (beq, ..., bnei) executed
9 Not taken conditional branch (beq, ..., bnei) executed
10 Data request from instruction cache
11 Hit in instruction cache
12 Read data requested from data cache
13 Read data hit in data cache
14 Write data request to data cache
15 Write data hit in data cache
16 Load (lbu, ..., lwx) with r1 as operand executed
17 Store (sb, ..., swx) with r1 as operand executed
18 Logical operation (and, andn, or, xor) executed
19 Arithmetic operation (add, idiv, mul, rsub) executed
20 Multiply operation (mul, mulh, mulhu, mulhsu, muli)
21 Barrel shifter operation (bsrl, bsra, bsll) executed
22 Shift operation (sra, src, srl) executed
23 Exception taken
24 Interrupt occurred
25 Pipeline stalled due to operand fetch stage (OF)
26 Pipeline stalled due to execute stage (EX)
27 Pipeline stalled due to memory stage (MEM)
28 Integer divide (idiv, idivu) executed
57 Interrupt latency from input to interrupt vector
58 Data cache latency for memory read
59 Data cache latency for memory write
60 Instruction cache latency for memory read
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Description
Event Counter events
Latency and Event Counter events
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Event Description
29 Floating point (fadd, ..., fsqrt)
30 Number of clock cycles
31 Immediate (imm) executed
32 Pattern compare (pcmpbf, pcmpeq, pcmpne)
33 Sign extend instructions (sext8, sext16) executed
34 Instruction cache invalidate (wic) executed
35 Data cache invalidate or flush (wdc) executed
36 Machine status instructions (msrset, msrclr)
37 Unconditional branch with delay slot executed
38 Taken conditional branch with delay slot executed
39 Not taken conditional branch with delay slot
40 Delay slot with no operation instruction executed
41 Load instruction (lbu, ..., lwx) executed
42 Store instruction (sb, ..., swx) executed
43 MMU data access request
44 Conditional branch (beq, ..., bnei) executed
45 Branch (br, bri, brk, brki, beq, ..., bnei) executed
46 Read or write data request from/to data cache
47 Read or write data cache hit
48 MMU exception taken
49 MMU instruction side exception taken
50 MMU data side exception taken
51 Pipeline stalled
52 Branch target cache hit for a branch or return
53 MMU instruction side access request
54 MMU instruction TLB (ITLB) hit
55 MMU data TLB (DTLB) hit
56 MMU unified TLB (UTLB) hit
61 MMU address lookup latency
62 Peripheral AXI interface data read latency
63 Peripheral AXI interface data write latency
91
Send Feedback