Xilinx MicroBlaze Reference Manual page 202

brk
Break
brk rD, rB
1 0 0 1 1 0
0 6
Description
Branch and link to the instruction located at address value in rB. The current value of PC will be
stored in rD. The BIP flag in the MSR will be set, and the reservation bit will be cleared.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This
means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
←
(rD) PC
←
PC (rB)
MSR[BIP]
Reservation
Registers Altered
• rD
• PC
• MSR[BIP]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 3 cycles
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD 0 1 1 0 0
11
00111
← 1
← 0
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
16 21 31
202
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