Chapter 3: Designing With The Core; General Design Guidelines; Clocking - Xilinx LogiCORE IP AXI Product Manual

Designing with the Core
This chapter includes guidelines and additional information to make designing with the
core easier.

General Design Guidelines

The Xilinx® Vivado® Design Suite has been optimized to provide a starting point for
designing with the AXI Bridge for PCI Express® core.

Clocking

Figure 3-1 shows the clocking diagram for the core. The main memory mapped AXI4 bus
clock axi_aclk is driven by axi_aclk_out.
X-Ref Target - Figure 3-1
axi_aclk_out and axi_ctl_aclk_out are connected to axi_aclk and
IMPORTANT:
axi_ctl_aclk, respectively, and they do not need to be connected in the design.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 3-1: Clocking Diagram
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Chapter 3
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