Xilinx MicroBlaze Reference Manual page 73

To inform the Interrupt Controller of the interrupt handling events,
• 01 - when MicroBlaze jumps to the interrupt handler code,
• 10 - when the RTID instruction is executed to return from interrupt,
• 11 - when MSR[IE] is changed from 0 to 1, which enables interrupts again.
The
Interrupt_Ack
Latency
The time it takes MicroBlaze to enter an Interrupt Service Routine (ISR) from the time an
interrupt occurs, depends on the configuration of the processor and the latency of the
memory controller storing the interrupt vectors. If MicroBlaze is configured to have a
hardware divider, the largest latency happens when an interrupt occurs during the
execution of a division instruction.
With low-latency interrupt mode, the time to enter the ISR is significantly reduced, since
the interrupt vector for each individual interrupt is directly supplied by the Interrupt
Controller. With compiler support for fast interrupts, there is no need for a common ISR at
all. Instead, the ISR for each individual interrupt will be directly called, and the compiler
takes care of saving and restoring registers used by the ISR.
Equivalent Pseudocode
←
r14 PC
if C_USE_INTERRUPT = 2
←
PC Interrupt_Address
Interrupt_Ack
else
←
PC C_BASE_VECTORS + 0x00000010
←
MSR[IE]
←
MSR[UMS]
Reservation
User Vector (Exception)
The user exception vector is located at address 0x8. A user exception is caused by inserting
a 'BRALID Rx,0x8' instruction in the software flow. Although Rx could be any general
purpose register, Xilinx recommends using R15 for storing the user exception return
address, and to use the RTSD instruction to return from the user exception handler.
Pseudocode
←
rx PC
←
PC C_BASE_VECTORS + 0x00000008
←
MSR[UMS]
Reservation
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
output port is active during one clock cycle, and is then reset to 00.
←
01
0
←
MSR[UM], MSR[UM]
←
0
←
MSR[UM], MSR[UM]
←
0
www.xilinx.com
Chapter 2: MicroBlaze Architecture
←
0, MSR[VMS] MSR[VM], MSR[VM]
←
0, MSR[VMS] MSR[VM], MSR[VM]
is set to:
Interrupt_Ack
←
0
←
0
73
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