Xilinx MicroBlaze Reference Manual page 226

lhu
Load Halfword Unsigned
lhu rD, rA, rB
lhur rD, rA, rB
lhuea rD, rA, rB
1 1 0 0 0 1
0 6
Description
Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the
contents of registers rA and rB. The data is placed in the least significant halfword of register rD and
the most significant halfword in rD is cleared.
If the R bit is set, a halfword reversed memory location is used and the two bytes in the halfword are
reversed, loading data with the opposite endianness of the endianness defined by the E bit (if virtual
protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
An unaligned data access exception occurs if the least significant bit in the address is not zero.
Pseudocode
if EA = 1 then
← (
Addr rA) & (rB)
else
←
Addr (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if Addr[31]
←
ESR[EC]
else
(rD)[16:31]
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
11
←
10010;ESR[S] 0
← ←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
←
00001; ESR[W] 0; ESR[S]
←
Mem(Addr); (rD)[0:15]
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 R 0 EA 0 0 0 0 0 0 0
16 21
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
1
←
MSR[VM]; MSR[UM] 0; MSR[VM]
← ←
0; ESR[Rx]
←
0
31
←
0
←
0
rD
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