Xilinx MicroBlaze Reference Manual page 261

sb
Store Byte
sb
sbr
sbea
1 1 0 1 0 0
0 6
Description
Stores the contents of the least significant byte of register rD, into the memory location that
results from adding the contents of registers rA and rB.
If the R bit is set, a byte reversed memory location is used, storing data with the opposite
endianness of the endianness defined by the E bit (if virtual protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of
adding them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation
entry corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by
no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
Pseudocode
if EA = 1 then
← (
Addr
else
←
Addr
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
MSR[UMS]
else
Mem(Addr)
Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
Latency
• 1 cycle with
• 2 cycles with
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, rB
rD, rA, rB
rD, rA, rB
rD rA
11
rA) & (rB)
(rA) + (rB)
← ←
10010;ESR[S] 1
←
MSR[UM]; MSR[VMS]
← ←
10000;ESR[S] 1; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
← (
rD)[24:31]
=0
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 R 0 EA 0 0 0 0 0 0 0
16 21
← ←
MSR[VM]; MSR[UM]
←
No-access-allowed
← ←
MSR[VM]; MSR[UM]
=1
←
0; MSR[VM] 0
←
0; MSR[VM] 0
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