Xilinx MicroBlaze Reference Manual page 157

Table 3-16: Mapping of Trace MSR
Trace_MSR_Reg
Bit
7
8
9
10
11
12
13
14
Table 3-17: Type of Trace Exception
Trace_Exception_Kind [0:4]
00000
00001
00010
00011
00100
00101
00110
00111
01010
01011
01100
10000
10001
10010
10011
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Machine Status Register
Bit Name
24 DCE Data Cache Enable
25 DZO Division by Zero or Division Overflow
26 ICE Instruction Cache Enable
27 FSL AXI4-Stream Error
28 BIP Break in Progress
29 C Arithmetic Carry
30 IE Interrupt Enable
31 Reserved Reserved
Stream exception
Unaligned exception
Illegal Opcode exception
Instruction Bus exception
Data Bus exception
Divide exception
FPU exception
Privileged instruction exception
Interrupt
External non maskable break
External maskable break
Data storage exception
Instruction storage exception
Data TLB miss exception
Instruction TLB miss exception
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