Xilinx MicroBlaze Reference Manual page 24

Machine Status Register (MSR)
The Machine Status Register contains control and status bits for the processor. It can be
read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry
copy. MSR can be written using either an MTS instruction or the dedicated MSRSET and
MSRCLR instructions.
When writing to the MSR using MSRSET or MSRCLR, the Carry bit takes effect immediately
and the remaining bits take effect one clock cycle later. When writing using MTS, all bits
take effect one clock cycle later. Any value written to bit 0 is discarded.
When used with an MTS or MFS instruction, the MSR is specified by setting Sx = 0x0001.
Figure 2-4 illustrates the MSR register and
values.
0
↑
CC
Table 2-9: Machine Status Register (MSR)
Bits Name
0 CC
1:16 Reserved
17 VMS
18 VM
19 UMS
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
↑
RESERVED
Figure 2-4: MSR
Arithmetic Carry Copy
Copy of the Arithmetic Carry (bit 29). CC is always the same as bit C.
Virtual Protected Mode Save
Only available when configured with an MMU
(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0)
Read/Write
Virtual Protected Mode
0 = MMU address translation and access protection disabled, with
C_USE_MMU = 3 (Virtual). Access protection disabled with
C_USE_MMU = 2 (Protection)
1 = MMU address translation and access protection enabled, with
C_USE_MMU = 3 (Virtual). Access protection enabled, with
C_USE_MMU = 2 (Protection).
Only available when configured with an MMU
(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0)
Read/Write
User Mode Save
Only available when configured with an MMU
(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0)
Read/Write
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Chapter 2: MicroBlaze Architecture
Table 2-9 provides the bit description and reset
17 18 19 20 21 22 23
↑ ↑ ↑ ↑ ↑ ↑ ↑
VMS VM UMS UM PVR EIP EE
Description
24 25 26 27 28 29 30 31
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
DCE DZO ICE FSL BIP C IE RES
Reset Value
0
0
0
0
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