Xilinx MicroBlaze Reference Manual page 39

Table 2-23: Translation Look-Aside Buffer Index Search Register (TLBSX)
Bits Name
0:21 VPN
22:31 Reserved
Processor Version Register (PVR)
The Processor Version Register is controlled by the C_PVR configuration option on
MicroBlaze.
• When
C_PVR
MSR[PVR]=0.
• When
C_PVR
if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented.
When read with the MFS or MFSE instruction the PVR is specified by setting Sa = 0x200x,
with x being the register number between 0x0 and 0xB.
With extended data addressing is enabled (parameter
significant bits of PVR8 and PVR9 are read with the MFS instruction, and the most
significant bits with the MFSE instruction.
Table 2-24 through
Table 2-24: Processor Version Register 0 (PVR0)
Bits Name
0 CFG
1 BS
2 DIV
3 MUL
4 FPU
5 EXC
6 ICU
7 DCU
8 MMU
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Virtual Page Number
This field represents the page number portion of the virtual memory
address. It is compared with the page number portion of the virtual
memory address under the control of the SIZE field, in each of the
Translation Look-Aside Buffer entries that have the V bit set to 1.
If the virtual page number is found, the TLBX register is written with
the index of the TLB entry and the MISS bit in TLBX is cleared to 0. If
the virtual page number is not found in any of the TLB entries, the
MISS bit in the TLBX register is set to 1.
Write Only
is set to 0 (None) the processor does not implement any PVR and
is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and
Table 2-35 provide bit descriptions and values.
Description
PVR implementation:
0 = Basic, 1 = Full
Use barrel shifter
Use divider
Use hardware multiplier
Use FPU
Use any type of exceptions
Use instruction cache
Use data cache
Use MMU
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Chapter 2: MicroBlaze Architecture
Description
C_ADDR_SIZE
Based on C_PVR
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
C_USE_FPU > 0 (None)
Based on C_*_EXCEPTION
Also set if C_USE_MMU > 0 (None)
C_USE_ICACHE
C_USE_DCACHE
C_USE_MMU > 0 (None)
Reset Value
> 32), the 32 least
Value
39
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