Xilinx MicroBlaze Reference Manual page 72

Register (MSR) is set to 1. On an interrupt, the instruction in the execution stage completes
while the instruction in the decode stage is replaced by a branch to the interrupt vector.
This is either address
address supplied by the Interrupt Controller.
The interrupt return address (the PC associated with the instruction in the decode stage at
the time of the interrupt) is automatically loaded into general purpose register R14. In
addition, the processor also disables future interrupts by clearing the IE bit in the MSR. The
IE bit is automatically set again when executing the RTID instruction.
Interrupts are ignored by the processor if either of the break in progress (
in progress (
EIP
By using the parameter
level-sensitive or edge-sensitive:
• When using level-sensitive interrupts, the
MicroBlaze has taken the interrupt, and jumped to the interrupt vector. Software must
clear the interrupt before returning from the interrupt handler. If not, the interrupt is
taken again, as soon as interrupts are enabled when returning from the interrupt
handler.
• When using edge-sensitive interrupts, MicroBlaze detects and latches the
input edge, which means that the input only needs to be asserted one clock cycle. The
interrupt input can remain asserted, but must be deasserted at least one clock cycle
before a new interrupt can be detected. The latching of an edge sensitive interrupt is
independent of the IE bit in MSR. Should an interrupt occur while the IE bit is 0, it will
immediately be serviced when the IE bit is set to 1.
Low-latency Interrupt Mode
A low-latency interrupt mode is available, which allows the Interrupt Controller to directly
supply the interrupt vector for each individual interrupt (via the
port).
The address of each fast interrupt handler must be passed to the Interrupt Controller when
initializing the interrupt system. When a particular interrupt occurs, this address is supplied
by the Interrupt Controller, which allows MicroBlaze to directly jump to the handler code.
With this mode, MicroBlaze also directly sends the appropriate interrupt acknowledge to
the Interrupt Controller (via the
responsibility of the Interrupt Service Routine to acknowledge level sensitive interrupts at
the source.
This information allows the Interrupt Controller to acknowledge interrupts appropriately,
both for level-sensitive and edge-triggered interrupt.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_BASE_VECTORS
) bits in the MSR are set to 1.
C_INTERRUPT_IS_EDGE
Interrupt_Ack
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Chapter 2: MicroBlaze Architecture
+ 0x10, or with low-latency interrupt mode, the
, the external interrupt can either be set to
input must remain set until
Interrupt
output port), although it is still the
) or exception
BIP
Interrupt
input
Interrupt_Address
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