Xilinx MicroBlaze Reference Manual page 66

Reset
When a
Reset
instructions from the reset vector (address 0x0). Both external reset signals are active high
and should be asserted for a minimum of 16 cycles.
Equivalent Pseudocode
←
PC C_BASE_VECTORS + 0x00000000
←
MSR C_RESET_MSR (see
←
EAR 0; ESR
←
PID 0; ZPR
Reservation
Hardware Exceptions
MicroBlaze can be configured to trap the following internal error conditions: illegal
instruction, instruction and data bus error, and unaligned access. The divide exception can
only be enabled if the processor is configured with a hardware divider (
configured with a hardware floating point unit (
floating point specific exceptions: underflow, overflow, float division-by-zero, invalid
operation, and denormalized operand error.
When configured with a hardware Memory Management Unit, it can also trap the following
memory management specific exceptions: Illegal Instruction Exception, Data Storage
Exception, Instruction Storage Exception, Data TLB Miss Exception, and Instruction TLB Miss
Exception.
A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware
exception vector (address
exception cycle is not executed.
The exception also updates the general purpose register R17 in the following manner:
• For the MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data
TLB Miss Exception, Instruction TLB Miss Exception) the register R17 is loaded with the
appropriate program counter value to re-execute the instruction causing the exception
upon return. The value is adjusted to return to a preceding
exception is caused by an instruction in a branch delay slot, the value is adjusted to
return to the branch instruction, including adjustment for a preceding
if any.
• For all other exceptions the register R17 is loaded with the program counter value of
the subsequent instruction, unless the exception is caused by an instruction in a branch
delay slot. If the exception is caused by an instruction in a branch delay slot, the
1. Reset input controlled by the debugger via MDM.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
(1)
or occurs, MicroBlaze flushes the pipeline and starts fetching
Debug_Rst
"MicroBlaze Core Configurability" in Chapter
← ←
0; FSR 0
← ←
0; TLBX 0
←
0
C_BASE_VECTORS
www.xilinx.com
Chapter 2: MicroBlaze Architecture
), it can also trap the following
C_USE_FPU>0
+ 0x20). The execution stage instruction in the
IMM
3)
). When
C_USE_DIV=1
instruction, if any. If the
instruction,
IMM
66
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