Chapter 3: Microblaze Signal Interface Description; Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze Signal Interface Description
This chapter describes the types of signal interfaces that can be used to connect
MicroBlaze™.

Overview

The MicroBlaze core is organized as a Harvard architecture with separate bus interface units
for data and instruction accesses. The following two memory interfaces are supported:
Local Memory Bus (LMB), and the AMBA® AXI4 interface (AXI4) and ACE interface (ACE).
The LMB provides single-cycle access to on-chip dual-port block RAM. The AXI4 interfaces
provide a connection to both on-chip and off-chip peripherals and memory. The ACE
interfaces provide cache coherent connections to memory. MicroBlaze also supports up to
16 AXI4-Stream interface ports, each with one master and one slave interface.
Features
MicroBlaze can be configured with the following bus interfaces:
• The AMBA AXI4 Interface for peripheral interfaces, and the AMBA AXI4 or AXI
Coherency Extension (ACE) Interface for cache interfaces (see ARM® AMBA® AXI and
ACE Protocol Specification,
• LMB provides simple synchronous protocol for efficient block RAM transfers
• AXI4-Stream provides a fast non-arbitrated streaming communication mechanism
• Debug interface for use with the Microprocessor Debug Module (MDM) core
• Trace interface for performance analysis
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
ARM IHI 0022E).
www.xilinx.com
Chapter 3
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