Xilinx MicroBlaze Reference Manual page 27

• An M_AXI_DP exception that specifies the failing AXI4 data access address
• A data storage exception that specifies the (virtual) effective address accessed
• An instruction storage exception that specifies the (virtual) effective address read
• A data TLB miss exception that specifies the (virtual) effective address accessed
• An instruction TLB miss exception that specifies the (virtual) effective address read
The contents of this register is undefined for all other exceptions. When read with the MFS
or MFSE instruction, the EAR is specified by setting Sa = 0x0003. The EAR register is
illustrated in Figure 2-5
With extended data addressing is enabled (parameter
significant bits of the register are read with the MFS instruction, and the most significant
bits with the MFSE instruction.
0
Table 2-10: Exception Address Register (EAR)
Bits
0:C_ADDR_SIZE-1
Exception Status Register (ESR)
The Exception Status Register contains status bits for the processor. When read with the
MFS instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated
in Figure 2-6, Table 2-11
the Exception Specific Status (ESS).
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
and Table 2-10 provides bit descriptions and reset values.
Figure 2-5: EAR
Name
EAR Exception Address Register
provides bit descriptions and reset values, and
↑
RESERVED
Figure 2-6: ESR
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Chapter 2: MicroBlaze Architecture
C_ADDR_SIZE
↑
EAR
Description
19 20
↑
DS
> 32), the 32 least
C_ADDR_SIZE - 1
Reset Value
0
Table 2-12 provides
26 27
↑ ↑
ESS EC
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31
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