Xilinx MicroBlaze Reference Manual page 112

The self-test example can be found in the standalone BSP BRAM driver source code,
typically in the subdirectory
Scrubbing
Scrubbing Methods
Scrubbing is performed using specific methods for the different block RAMs:
• Instruction and data caches: All lines in the caches are cyclically invalidated using the
WIC and WDC instructions respectively. This forces the cache to reload the cache line
from external memory.
• Memory Management Unit UTLB: All entries in the UTLB are cyclically invalidated by
writing the TLBHI register with the valid bit cleared.
• Branch Target Cache: The entire BTC is invalided by doing a synchronizing branch, BRI 4.
• LMB block RAM: All addresses in the memory are cyclically read and written, thus
correcting any single bit errors on each address.
It is also possible to add interrupts for correctable errors from the LMB BRAM Interface
Controllers, and immediately scrub this address in the interrupt handler, although in most
cases it only improves reliability slightly.
The failing address can be determined by reading the Correctable Error First Failing Address
Register in each of the LMB BRAM Interface Controllers. To be able to generate an interrupt
C_ECC_STATUS_REGISTERS
Controllers, and to read the failing address
Calculating Scrubbing Rate
The scrubbing rate depends on failure intensity and desired reliability.
The approximate equation to determine the LMB memory scrubbing rate is in our case
given by
P
≈
760
W
where P is the probability of an uncorrectable error in a memory word, BER is the soft error
W
rate for a single memory bit, and SR is the Scrubbing Rate.
The soft error rates affecting block RAM for each product family can be found in the Device
Reliability Report (UG116).
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
microblaze_0/libsrc/bram_v3_03_a/src/xbram_selftest.c
must be set to 1 in the connected LMB BRAM Interface
 
2
BER
 
----------- -
2
 
SR
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Chapter 2: MicroBlaze Architecture
C_CE_FAILING_REGISTERS
.
must be set to 1.
112
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