Microblaze I/O Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze I/O Overview

The core interfaces shown in
M_AXI_DP: Peripheral Data Interface, AXI4-Lite or AXI4 interface
M_AXI_IP: Peripheral Instruction interface, AXI4-Lite interface
M0_AXIS..M15_AXIS: AXI4-Stream interface master direct connection interfaces
S0_AXIS..S15_AXIS: AXI4-Stream interface slave direct connection interfaces
M_AXI_DC: Data side cache AXI4 interface
M_ACE_DC: Data side cache AXI Coherency Extension (ACE) interface
M_AXI_IC: Instruction side cache AXI4 interface
M_ACE_IC: Instruction side cache AXI Coherency Extension (ACE) interface
Instruction-side
bus interface
M_AXI_IC
M_ACE_IC
M_AXI_IP
Bus
IF
ILMB
Optional MicroBlaze feature
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Figure 3-1
DLMB: Data interface, Local Memory Bus (BRAM only)
ILMB: Instruction interface, Local Memory Bus (BRAM only)
Core: Miscellaneous signals for: clock, reset, interrupt, debug, trace
Memory Management Unit (MMU)
ITLB
Program
Counter
Special
Purpose
Registers
Branch
Target
Cache
Instruction
Buffer
Instruction
Decode
Figure 3-1: MicroBlaze Core Block Diagram
www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
and the following Table 3-1
UTLB
DTLB
ALU
Shift
Barrel Shift
Multiplier
Divider
FPU
Register File
32 X 32b
are defined as follows:
Data-side
bus interface
M_AXI_DC
M_ACE_DC
M_AXI_DP
Bus
IF
DLMB
M0_AXIS..
M15_AXIS
S0_AXIS..
S15_AXIS
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