Xilinx MicroBlaze Reference Manual page 168

Table 3-18: Configuration Parameters (Cont'd)
Parameter Name
C_STREAM_INTERCONNECT
C_Mn_AXIS_PROTOCOL
C_Sn_AXIS_PROTOCOL
C_Mn_AXIS_DATA_WIDTH
C_Sn_AXIS_DATA_WIDTH
1. The 7 least significant bits must all be 0.
2. Not all sizes are permitted in all architectures. The cache uses between 0 and 32 RAMB primitives (0 if cache size is less than
2048).
3. Not available when C_AREA_OPTIMIZED is set to 1 (Area).
Table 3-19: Parameter C_FAMILY Allowable Values
Artix aartix7 artix7 artix7l qartix7 qartix7l
Kintex kintex7 kintex7l qkintex7 qkintex7l kintexu kintexuplus
Virtex qvirtex7 virtex7 virtexu virtexuplus
Zynq azynq zynq qzynq zynquplus
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Select AXI4-Stream
interconnect
AXI4-Stream protocol
AXI4-Stream protocol
AXI4-Stream master
data width
AXI4-Stream slave data
width
Allowable Values
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Tool
Allowable Default
Assign
Values Value
ed
0,1 0
GENERIC GENERIC
GENERIC GENERIC
NA
32 32
NA
32 32
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VHDL Type
integer
string
string
integer
integer
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