Xilinx MicroBlaze Reference Manual page 198

br
Unconditional Branch
br rB
bra rB
brd rB
brad rB
brld rD, rB
brald rD, rB
1 0 0 1 1 0
0 6
Description
Branch to the instruction located at address determined by rB.
The mnemonics brld and brald will set the L bit. If the L bit is set, linking will be performed. The
current value of PC will be stored in rD.
The mnemonics bra, brad and brald will set the A bit. If the A bit is set, it means that the branch is to
an absolute value and the target is the value in rB, otherwise, it is a relative branch and the target will
be PC + rB.
The mnemonics brd, brad, brld and brald will set the D bit. The D bit determines whether there is a
branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following the branch (that is, in the branch delay slot) is allowed to complete execution before
executing the target instruction.
If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the
branch is the target instruction.
Pseudocode
if L = 1 then
←
(rD) PC
if A = 1 then
←
PC (rB)
else
←
PC PC + (rB)
if D = 1 then
allow following instruction to complete execution
Registers Altered
• rD
• PC
Latency
• 2 cycles (if the D bit is set)
• 3 cycles (if the D bit is not set)
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Branch
Branch Absolute
Branch with Delay
Branch Absolute with Delay
Branch and Link with Delay
Branch Absolute and Link with Delay
rD D A L 0 0
1
1
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
3
1
198
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