Xilinx MicroBlaze Reference Manual page 113

Use Cases
Several common use cases are described here. These use cases are derived from the
LogiCore IP Processor LMB BRAM Interface Controller (PG112) product guide.
Minimal
This system is obtained when enabling fault tolerance in MicroBlaze, without doing any
other configuration.
The system is suitable when area constraints are high, and there is no need for testing of the
ECC function, or analysis of error frequency and location. No ECC registers are
implemented. Single bit errors are corrected by the ECC logic before being passed to
MicroBlaze. Uncorrectable errors set an error signal, which generates an exception in
MicroBlaze.
Small
This system should be used when it is necessary to monitor error frequency, but there is no
need for testing of the ECC function. It is a minimal system with Correctable Error Counter
Register added to monitor single bit error rates. If the error rate is too high, the scrubbing
rate should be increased to minimize the risk of a single bit error becoming an
uncorrectable double bit error. Parameters set are
Typical
This system represents a typical use case, where it is required to monitor error frequency, as
well as generating an interrupt to immediately correct a single bit error through software. It
does not provide support for testing of the ECC function. It is a small system with
Correctable Error First Failing registers and Status register added. A single bit error will latch
the address for the access into the Correctable Error First Failing Address Register and set
the CE_STATUS bit in the ECC Status Register. An interrupt will be generated triggering
MicroBlaze to read the failing address and then perform a read followed by a write on the
failing address. This will remove the single bit error from the BRAM, thus reducing the risk
of the single bit error becoming a uncorrectable double bit error. Parameters set are
= 1,
C_CE_COUNTER_WIDTH
= 1.
Full
This system uses all of the features provided by the LMB BRAM Interface Controller, to
enable full error injection capability, as well as error monitoring and interrupt generation. It
is a typical system with Uncorrectable Error First Failing registers and Fault Injection
registers added. All features are switched on for full control of ECC functionality for system
debug or systems with high fault tolerance requirements. Parameters set are
C_CE_COUNTER_WIDTH
C_UE_FAILING_REGISTERS
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
= 10,
C_ECC_STATUS_REGISTER
= 10,
C_ECC_STATUS_REGISTER
= 1 and
C_FAULT_INJECT
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Chapter 2: MicroBlaze Architecture
= 1 and
C_ECC C_CE_COUNTER_WIDTH
= 1 and
C_CE_FAILING_REGISTERS
= 1 and
C_CE_FAILING_REGISTERS
= 1.
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= 10.
C_ECC
= 1,
C_ECC
= 1,
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