Xilinx MicroBlaze Reference Manual page 162

Table 3-18: Configuration Parameters (Cont'd)
Parameter Name
C_DEBUG_EXTERNAL_TRACE
C_ASYNC_INTERRUPT
C_ASYNC_WAKEUP
C_INTERRUPT_IS_EDGE
C_EDGE_IS_POSITIVE
C_FSL_LINKS
C_USE_EXTENDED_FSL_INSTR
C_ICACHE_BASEADDR
C_ICACHE_HIGHADDR
C_USE_ICACHE
C_ALLOW_ICACHE_WR
C_ICACHE_LINE_LEN
C_ICACHE_ALWAYS_USED
C_ICACHE_FORCE_TAG_LUTRAM
C_ICACHE_STREAMS
C_ICACHE_VICTIMS
C_ICACHE_DATA_WIDTH
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
External Program Trace
Asynchronous Interrupt
Asynchronous Wakeup
Level/Edge Interrupt
Negative/Positive Edge
Interrupt
Number of AXI-Stream
interfaces
Enable use of extended
stream instructions
Instruction cache base
address
Instruction cache high
address
Instruction cache
Instruction cache write
enable
Instruction cache line
length
Instruction cache
interface used for all
memory accesses in the
cacheable range
Instruction cache tag
always implemented
with distributed RAM
Instruction cache
streams
Instruction cache
victims
Instruction cache data
width
0 = 32 bits
1 = Full cache line
2 = 512 bits
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Tool
Allowable Default
Assign
Values Value
0,1 0
0,1 0
00,01,10,11 00
0, 1 0
0, 1 1
0-16 0
0, 1 0
0x00000000 0x0000
- 0xFFFFFFFF 0000
0x00000000 0x3FFF
- 0xFFFFFFFF FFFF
0, 1 0
0, 1 1
4, 8, 16 4
0, 1 1
0, 1 0
0, 1 0
0, 2, 4, 8 0
0, 1, 2 0
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VHDL Type
ed
yes
integer
yes
integer
yes
integer
yes
integer
integer
yes
integer
integer
std_logic_vector
std_logic_vector
integer
integer
integer
integer
integer
integer
integer
integer
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