Xilinx MicroBlaze Reference Manual page 263

sbi
Store Byte Immediate
sbi
1 1 1 1 0 0
0 6
Description
Stores the contents of the least significant byte of register rD, into the memory location that
results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation
entry corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by
no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
Pseudocode
←
(rA) + sext(IMM)
Addr
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
MSR[UMS]
else
Mem(Addr)
Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
Latency
• 1 cycle with
• 2 cycles with
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B
instruction with an imm instruction. See the instruction
bit immediate values.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, IMM
rD rA
11
← ←
10010;ESR[S] 1
←
MSR[UM]; MSR[VMS]
← ←
10000;ESR[S] 1; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
← (
rD)[24:31]
=0
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
16
← ←
MSR[VM]; MSR[UM]
←
No-access-allowed
← ←
MSR[VM]; MSR[UM]
=1
"imm," page 222
IMM
←
0; MSR[VM] 0
←
0; MSR[VM] 0
for details on using 32-
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