Xilinx MicroBlaze Reference Manual page 57

TLB Entry Format
Figure 2-20 shows the format of a TLB entry. Each TLB entry is 68 bits and is composed of
two portions: TLBLO (also referred to as the data entry), and TLBHI (also referred to as the
tag entry).
TLBLO:
0
TLBHI:
0
The TLB entry contents are described in
The fields within a TLB entry are categorized as follows:
• Virtual-page identification (TAG, SIZE, V, TID)—These fields identify the page-
translation entry. They are compared with the virtual-page number during the
translation process.
• Physical-page identification (RPN, SIZE)—These fields identify the translated page in
physical memory.
• Access control (EX, WR, ZSEL)—These fields specify the type of access allowed in the
page and are used to protect pages from improper accesses.
• Storage attributes (W, I, M, G, E, U0)—These fields specify the storage-control
attributes, such as caching policy for the data cache (write-back or write-through),
whether a page is cacheable, and how bytes are ordered (endianness).
Table 2-37 shows the relationship between the TLB-entry
size. This table also shows how the page size determines which address bits are involved in
a tag comparison, which address bits are used as a page offset, and which bits in the
physical page number are used in the physical address.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
↑
RPN
↑
TAG
Figure 2-20: TLB Entry Format
Table 2-20, page 35
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Chapter 2: MicroBlaze Architecture
22 23 24 28 29 30 31
↑ ↑ ↑ ↑ ↑ ↑ ↑
EX WR ZSEL W
22 25 26 27 28
↑ ↑ ↑ ↑
SIZE V E U0
and Table 2-21, page
field and the translated page
SIZE
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I M G
35
↑
TID
37.
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