Xilinx MicroBlaze Reference Manual page 145

32-bit soft processor
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Back-to-Back Write Operation
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Write_Strobe
Data_Read
Ready
Wait
CE
UE
Back-to-Back Read Operation
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Write_Strobe
Data_Read
Ready
Wait
CE
UE
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
A0
A1
BE0
BE1
D0
D1
Don't Care
Figure 3-6: LMB Back-to-Back Write Operation
A0
A1
D0
Don't Care
Figure 3-7: LMB Back-to-Back Read Operation
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A2
A3
BE2
BE3
D2
D3
Don't Care
A2
A3
D1
D2
Don't Care
A4
BE4
D4
Don't Care
A4
D3
D4
Don't Care
145
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