Xilinx MicroBlaze Reference Manual page 115

The outputs from the master MicroBlaze core drive the peripherals in the system. All data
leaving the protected area pass through inhibitors. Each inhibitor is controlled from its
associated comparator.
Each protected area of the design must be implemented in its own partition, using a
hierarchical Single Chip Cryptography (SCC) flow. A detailed explanation of this flow, and
further references, can be found in the document Hierarchical Design Methodology Guide
(UG748).
A block diagram of the system is shown in
MicroBlaze Partition
DLMB
BRAM Controller
BRAM
ILMB
BRAM Controller
MicroBlaze
Debug Module
MicroBlaze Partition
DLMB
BRAM Controller
BRAM
ILMB
BRAM Controller
Debug Interface - Removed for Production
Error Detection
The error detection use case requires that all transient and permanent faults are detected.
This is essential in fail safe and fault tolerant applications, where redundancy is utilized to
improve system availability.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_LOCKSTEP_SLAVE = 0
MicroBlaze
Master
Debug
Lockstep_Master_Out
Lockstep_Slave_In
Debug
MicroBlaze
Slave
C_LOCKSTEP_SLAVE = 1
Figure 2-41: Lockstep Tamper Protection Application
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Figure 2-41.
Outputs
Inputs
Comparator Partition
Lockstep_Out
Comparator
Inputs
Comparator Partition
Lockstep_Out
Comparator
Peripheral
Partition
I/O Interfaces
External Memory
Interfaces
115
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