Xilinx MicroBlaze Reference Manual page 142

Data_Read[0:31]
The read data bus is an input to the core and contains data read from memory. Data_Read
is valid on the rising edge of the clock when Ready is high.
Ready
The Ready signal is an input to the core and indicates completion of the current transfer
and that the next transfer can begin in the following clock cycle. It is sampled on the rising
edge of the clock. For reads, this signal indicates the Data_Read[0:31] bus is valid, and
for writes it indicates that the Data_Write[0:31] bus has been written to local memory.
Wait
The Wait signal is an input to the core and indicates that the current transfer has been
accepted, but not yet completed. It is sampled on the rising edge of the clock.
CE
The CE signal is an input to the core and indicates that the current transfer had a
correctable error. It is valid on the rising edge of the clock when Ready is high. For reads,
this signal indicates that an error has been corrected on the Data_Read[0:31] bus, and
for byte and halfword writes it indicates that the corresponding data word in local memory
has been corrected before writing the new data.
UE
The UE signal is an input to the core and indicates that the current transfer had an
uncorrectable error. It is valid on the rising edge of the clock when Ready is high. For reads,
this signal indicates that the value of the Data_Read[0:31] bus is erroneous, and for byte
and halfword writes it indicates that the corresponding data word in local memory was
erroneous before writing the new data.
Clk
All operations on the LMB are synchronous to the MicroBlaze core clock.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
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