Adding The Perf_Axi Core - Xilinx MicroBlaze ML605 Hardware Tutorial

Axi interface based processor subsystem

Hide thumbs Also See for MicroBlaze ML605:

Table of Contents

System Design Flow

Adding the Perf_AXI core

In the Project Information Area of the XPS GUI, click the IP Catalog tab.

Expand the Project Local PCores by clicking the respective +. Expand the USER by

clicking the respective +. Right-click on PERF_AXI and select Add IP.

Inside the XPS Core Config dialog box, set C_BASEADDR to 0x90000000 and

C_HIGHADDR to 0x9000FFFF.

The C_MSTID and C_MSTID_WIDTH are dependent on the connection of the

AXI_CDMA master to the AXI interconnect. The C_MSTID_WIDTH is the size of the

signal for both ARVALID and ARREADY signals which depend on the number of

masters connected to the interconnect. Each master uses 1 bit of these signals. The

C_MSTID identifies the master's bit for the ARVALID and ARREAD signals.

•

For ML605:

Set C_MSTID to 5 and C_MSTID_WIDTH to 6.

•

For SP605:

Set C_MSTID to 2 and C_MSTID_WIDTH to 3.

Click OK.

In the Instantiate and Connect IP dialog box, select User will make necessary

connections and settings and click OK. (Connecting bus interfaces are discussed

later in this tutorial.)

www.xilinx.com

ML605/SP605 Hardware Tutorial

UG669 (v3.0) March 15, 2011

Table of Contents

Microblaze sp605