Xilinx MicroBlaze Reference Manual page 68

to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the
address. In all other cases the response is ignored.
The instructions side local memory (ILMB) can only cause instruction bus exception
¨
when either an uncorrectable error occurs in the LMB memory, as indicated by the
signal, or
IUE
the LMB memory, as indicated by the
• Illegal Opcode Exception
The illegal opcode exception is caused by an instruction with an invalid major opcode
(bits 0 through 5 of instruction). Bits 6 through 31 of the instruction are not checked.
Optional processor instructions are detected as illegal if not enabled. If the optional
feature
C_OPCODE_0x0_ILLEGAL
the instruction is equal to 0x00000000.
• Data Bus Exception
The data bus exception is caused by errors when reading data from memory or writing
data to memory.
The data peripheral AXI4 interface (M_AXI_DP) exception is caused by an error
¨
response on
The data cache AXI4 interface (M_AXI_DC) exception is caused by:
¨
- An error response on
-
OKAY
The exception can only occur when
is turned off, when an exclusive access using
Inhibit Caching bit is set for the address. In all other cases the response is ignored.
The data side local memory (DLMB) can only cause instruction bus exception when
¨
either an uncorrectable error occurs in the LMB memory, as indicated by the
signal, or
LMB memory, as indicated by the
accesses, and for byte and halfword write accesses.
• Unaligned Exception
The unaligned exception is caused by a word access where the address to the data bus
has bits 30 or 31 set, or a half-word access with bit 31 set.
• Divide Exception
The divide exception is caused by an integer division (idiv or idivu) where the divisor is
zero, or by a signed integer division (idiv) where overflow occurs (-2147483648 / -1).
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_ECC_USE_CE_EXCEPTION
is enabled, an illegal opcode exception is also caused if
or
M_AXI_DP_RRESP
M_AXI_DC_RRESP
response on
M_AXI_DC_RRESP
C_ECC_USE_CE_EXCEPTION
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Chapter 2: MicroBlaze Architecture
is set to 1 and a correctable error occurs in
signal.
ICE
.
M_AXI_DP_BRESP
or
M_AXI_DC_BRESP
in case of an exclusive access using
C_DCACHE_ALWAYS_USED
or
LWX SWX
is set to 1 and a correctable error occurs in the
signal. An error can occur for all read
DCE
,
LWX
is set to 1 and the cache
is performed, or if the MMU
DUE
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.
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